The present invention relates to an elastic buffer circuit, and more particularly to an elastic buffer circuit for use in a satellite communication receiving system of a time division multi-access (TDMA) type to adjust the timing between burst data signals from the satellite and signals handled by the ground communication system.
In transferring burst data signals, transmitted via a satellite, to a ground communication system, data signals demodulated by a demodulator should be converted into signals adapted to the timing of the ground communication system. In a satellite communication system or a mobile communication system, a clock signal recovered from burst data signals contains phase jitter, which should be absorbed on the receiving side of the satellite or mobile communication system before the signals are transferred to the ground communication system. An elastic buffer circuit is used in this timing conversion.
Into an elastic buffer circuit are entered from a demodulator a burst synchronization (sync) code having a unique word and data signals following it. A received recovered clock signal, extracted by the demodulator, is also entered into the elastic buffer circuit, which detects a burst sync code according to this received recovered clock signal and stores the data signals following this burst sync code into a data memory circuit built into the elastic buffer circuit. An address for writing the data signals into the data memory circuit is generated according to the received recovered clock signal.
Meanwhile, in accessing the data memory circuit from a terminal, the terminal supplies a read clock signal to the data memory circuit to read out the data signals stored therein In this manner, the burst data signals from the satellite are converted into signals adapted to the timing of the ground communication system.
In a satellite communication system, if the electromagnetic wave received from the satellite is weakened by rain-caused attenuation or the like, the clock signal may become lost. In the absence of the clock, the data signal whose time position corresponds to the lost clock will not be written into the data memory circuit. If such a clock loss occurs, even if the reception of the clock signal is restored to its normal level, there will arise a data shift in the position in the data memory circuit into which the data signal is written after the restoration of the clock. Thus every data signal after the clock loss is written into a wrong address of the data memory circuit to invite burst errors.